1. Field of the Invention
The present invention relates to semiconductor packages, packaging substrates and fabrication methods thereof, and, more particularly, to a wire-bonding semiconductor package, packaging substrate and fabrication method thereof.
2. Description of Related Art
For electrically connecting a semiconductor chip and a packaging substrate or a lead frame through bonding wires, the semiconductor chip has a plurality of electrode pads formed on a surface thereof and the packaging substrate has a plurality of wire bonding pads corresponding to the electrode pads, or the lead frame has a plurality of leads corresponding to the electrode pads. The semiconductor chip is mounted on a die attach area of the packaging substrate or the lead frame and the electrode pads of the semiconductor chip are electrically connected to the wire bonding pads or the leads through a plurality of bonding wires such that the semiconductor chip is electrically connected to the packaging substrate or the lead frame.
Generally, before a wire bonding process, a surface treatment layer made of, for example, Ni/Au is formed on the wire bonding pads of the packaging substrate for improving electrical bonding forces between gold wires and the wire bonding pads and avoiding oxidation of the wire bonding pads. The process for forming the surface treatment layer can be a process with plating lines or a process without plating lines.
FIGS. 1A and 1A′ show a conventional electroplating process with plating lines. Referring to the drawings, a substrate body 10 has a die attach area A and a circuit layer 11. The circuit layer 11 has a plurality of conductive traces 11a and a plurality of conductive vias 11b. One end of each of the conductive traces 11a has a wire bonding pad 110 disposed adjacent to the die attach area A, and the other end is disposed away from the die attach area A for connecting a corresponding one of the conductive vias 11b and further connecting an electroplating line 111 extending to an edge of the substrate body 10. Further, the electroplating lines 111 at each side of the substrate body 10 are connected to an electroplating bus (or referred to as a common electroplating line, not shown). An insulating protection layer 12 is formed on the substrate body 10, and a plurality of openings 120 are formed in the insulating protection layer 12 for exposing the wire bonding pads 110.
Then, a plurality of array-arranged substrate bodies 10 are disposed in an electroplating tub (not shown) and an electroplating process is performed such that current flows through the electroplating buses as well as the electroplating lines 111 to thereby form a surface treatment layer 14 on the wire bonding pads 110. Then, the electroplating buses are removed.
As described above, each of the conductive traces 11a is connected to an electroplating line 111. After the electroplating process, the electroplating lines 111 still remain on the edges of the substrate body 10. As such, when the packaging substrate 1 is applied to a high frequency product having high electrical performance, signal transmission in the conductive traces 11a can be adversely affected by the electroplating lines 111 such that cross-talk occurs, thereby resulting in signal distortion or poor electrical performance.
Accordingly, an NPL (Non-plating line) electroplating process is provided. Referring to Taiwan Patent No. I223426 or FIG. 1B, a conductive film 13 is formed on a substrate body 10′ and a first resist layer 12a is formed on the conductive film 13 such that an electroplating process is performed for forming a circuit layer 11′. Then, a second resist layer 12b is formed such that an electroplating process is performed through the conductive film 13 for forming a surface treatment layer 14′ on wire bonding pads 110′ of the circuit layer 11′. Thereafter, the first resist layer 12a, the second resist layer 12b and the conductive film 13 covered by the first and second resist layers 12a, 12b are removed. By using the conductive film 13 instead of a plurality of electroplating lines, cross-talk is avoidable.
However, in the NPL electroplating process, two patterning processes for patterning the resist layers are required. The resist layers and masks are high in material cost, and exposure and development processes are also high in equipment cost. Therefore, the NPL electroplating process is costly, time-consuming and does not meet cost-effective requirements.
To mount a semiconductor chip 16 on the packaging substrate, an adhesive layer 15 is formed on the insulating protection layer 12 in the die attach area A. Referring to FIG. 1A′, when the chip 16 is attached to the adhesive layer 15, the adhesive layer 15 is squeezed to overflow, thus polluting the wire bonding pads 110 around the die attach area A and adversely affecting the electrical connection of the packaging substrate 1.
In order to increase the distance D between the wire bonding pads 110 and the die attach area A so as to protect the wiring bonding pads 110 from being polluted by the adhesive material, the area of the substrate body 10 needs to be increased. As such, the packaging substrate 1 cannot meet the miniaturization requirement. Furthermore, since the layout space for the circuit layer 11 are reduced due to the provision of the electroplating lines, the flexibility of the circuit layout is reduced.
To increase the distance D between the wire bonding pads 110 and the die attach area A, the length of gold wires (not shown) also needs to be increased, thereby leading to a high material cost and a high fabrication cost.
Therefore, how to overcome the above-described drawbacks has become urgent.